1. Field of the Invention
The present invention relates to a semiconductor device, a method for manufacturing the same, and an electronic device, and particularly to a semiconductor device packaged by mounting a second semiconductor chip on a first semiconductor chip having an electronic circuit section such as a solid-state imaging element section or the like, a method for manufacturing the same, and an electronic device having the same.
2. Description of the Related Art
A package structure referred to as a chip-on-chip (CoC) package, which includes a plurality of semiconductor chips laminated and sealed within the single package to achieve miniaturization, high functionality and the like of a semiconductor device, has been put to practical use.
The CoC package is also applied to for example a structure in which a memory element and a processor element are laminated, and progress has been made in practical use of the CoC package as a SIP (System in Package) type semiconductor device.
For example, when an SIP is formed by a CoC package as in Japanese Patent Laid-Open No. 2008-192815 (hereinafter referred to as Patent Document 1), the application of flip chip connection is principally considered for connection between an upper semiconductor chip and a lower semiconductor chip.
In the case where flip chip connection is applied to connection between semiconductor chips in a CoC package, a first semiconductor chip (lower stage side semiconductor chip) is mounted on a wiring board having an external connection terminal and the like.
A second semiconductor chip (upper stage side semiconductor chip) is flip-chip-connected to the first semiconductor chip.
That is, electrical and mechanical connection between the first and second semiconductor chips is made by connecting a bump electrode provided on the upper surface of the first semiconductor chip and a bump electrode provided on the lower surface of the second semiconductor chip to each other.
Further, an underfill resin layer is filled into a gap between the first and second semiconductor chips to improve connection reliability and the like.
Japanese Patent Laid-Open Nos. 2005-276879, 2008-252027 and 2008-124140 (hereinafter referred to as Patent Document 2, 3 and 4, respectively), for example, disclose techniques for forming a dam that serves to stop the flow of the underfill resin layer in the case of the structure in which the gap between the first and second semiconductor chips of the CoC package is filled with the underfill resin layer.
The dam is intended mainly to prevent resin contamination caused by a flow of the underfill resin layer into an electronic circuit section such as an Al electrode formed in the first semiconductor chip in a peripheral part of a mounting region of the second semiconductor chip.
In the CoC package of the above-described constitution, a reactant gas is emitted from a fillet of the underfill resin layer, which fillet is formed at the peripheral part of the second semiconductor chip, at a time of resin curing reaction.
In Patent Documents 1 to 4, when a distance between the electronic circuit section such as the Al electrode and the like and the upper semiconductor chip is shortened to miniaturize the CoC package, the above-described gas contaminates the electronic circuit section such as the Al electrode and the like.
As a result, a failure in wire bonding and a degradation in reliability occur, and it is therefore difficult to miniaturize the CoC package.
In addition, in a case where a solid-state imaging element section is formed on the lower semiconductor chip, even when a dam is formed between the solid-state imaging element section and the upper semiconductor chip, the imaging element section is contaminated by the reactant gas emitted from the fillet of the above-described underfill resin layer, and thus an imaging characteristic is degraded.
In addition, a semiconductor device in which rewiring is formed on a glass substrate or the like and a semiconductor chip having a solid-state imaging section formed thereon is flip-chip-connected is under study.
In order to prevent a resin protecting a bump electrode from contaminating the light receiving surface of the solid-state imaging section, techniques for forming a dam between the bump electrode and the semiconductor chip having the solid-state imaging section formed thereon are under study.
However, reference to Japanese Patent Laid-Open Nos. 2007-533131, 2002-118207 and Hei 06-204442 (hereinafter referred Patent Document 5, 6 and 7, respectively) and the like shows that a dam made of a resin is formed on only the side of the glass substrate, and that there is a problem in a sealing property for the side of the semiconductor chip having the solid-state imaging section formed thereon.
In addition, this technique can essentially form a bump electrode only in a peripheral part of a laminated semiconductor chip or the semiconductor chip having a solid-state imaging section formed thereon.
Further, in semiconductor devices disclosed in Patent Documents 6 and 7, no dam is formed on the side of an Al electrode, and there is thus a fear of contamination of the Al electrode.